The present invention relates to an on-die termination (ODT) control circuit which controls an on-die termination used in a semiconductor memory, and more specifically, to an ODT control circuit which is synchronization with an external clock during power-down mode.
In recent years, as the operating speed of semiconductor memory devices has become faster, a swing width of signals interfaced between the semiconductor memory devices gradually decreases. The reason is to minimize the delay time required for signal transmission. However, as the swing width of signals decreases, external noise interference increases, and signal reflection due to impedance mismatching at an interface terminal becomes critical.
Such impedance mismatching may be caused by external noise, variation of power supply voltage, changes in operating temperature, and variations during manufacturing processes, and the like. Impedence mismatching negatively impacts high-speed data transmission and may distort output data.
Transmission of a distorted output signal frequently causes problems at the receiving side, such as setup/hold fail, erroneous input level determination, and the like.
In particular, in electronic products employing a dynamic random access memory (DRAM), high speed operation has led to a dramatic increase in the frequency of a signal bus. Accordingly, various bus termination techniques are being studied for minimizing the distortion of signal integrity by eliminating impedance mismatching. One study revealed that a method using on-die termination (ODT) rather than mother board termination (MBT) is more advantageous for signal integrity, particularly in an electronic system with a stub bas structure.
On-die termination means a termination structure in which bus termination is attained at an input/output (I/O) port of a memory device mounted on a memory module. As a result, such on-die termination is an impedance matching circuit, which is also referred to as on-chip termination, and is employed in the vicinity of pads in an integrated circuit chip.
FIG. 1 is a block diagram illustrating a configuration of an ODT control signal generation circuit according to the prior art.
Referring to FIG. 1, an ODT control circuit according to the prior art is configured by including a clock buffer unit 10 which receives an external clock signal CLK and buffers it to output an internal clock signal iCLK, a mode identification signal generation unit 20 which receives an ODT enabling signal ODTEN and a clock enabling signal CKE to output a mode identification signal CKEODT, an ODT buffer unit 30 which receives an ODT command signal and buffers it to output an internal ODT command signal iODT, a DLL control unit 40 which receives DLL clocks (RCKDLL, FCKDLL), the mode identification signal CKEODT and the ODT enable signal ODTEN, and delays and outputs the DLL clocks for a predetermined period of time, and an ODT control signal generation unit 50 which combines the internal clock iCLK, the internal ODT signal, the DLL signals outputted from the DLL control unit, and the ODT enable signal ODTEN to output an ODT control signal ODTLAT.
The DLL clock signals (RCKDLL, FCKDLL) are generated by a delay-locked loop (DLL) circuit and then inputted. The DLL circuit enables the synchronization of a clock signal used for the final input/output of data to be synchronized with an external clock signal by compensating for a clock delay component which occurs during a process in which a clock signal being outputted is transmitted to a data output terminal inside the semiconductor memory device to generate an internal clock, the detailed explanation of which will be omitted because any person skilled in the art can easily achieve the design and also it is not directly related to this invention. Furthermore, in this invention, the DLL clock includes a rising DLL clock (RCKDLL) and a failing DLL clock (FCKDLL). The rising DLL clock RCKDLL is a clock synchronized with the rising edge of the clock signal, and the falling DLL clock FCKDLL is a clock synchronized with the falling edge of the clock signal.
The mode identification signal generation unit 20 outputs a high or low level signal whether the semiconductor device is in power-down mode or not.
FIG. 2 is a circuit illustrating an internal configuration of the DLL control unit 40.
Referring to FIG. 2, the DLL control unit 40 includes a NAND gate 41 which receives the ODT enable signal ODTEN and the mode identification signal CKEODT to generate an ODT enable bar signal ODTENB, a NOR gate 42 which receives the ODT enabling bar signal ODTENB and the rising DLL clock signal RCKDLL, a NOR gate 43 which receives the ODT enable bar signal ODTENB and the falling DLL clock signal FCKDLL, a rising DLL clock output unit 44 which delays the output of the NOR gate 42 for a predetermined period of time to output a rising DLL clock, and a failing DLL clock output unit 45 which delays an output of the NOR gate 43 for a predetermined period of time to output a falling DLL clock.
The rising DLL clock output unit 44 outputs clock signals (RCKDLL10, RCKDLL20) having a different delay amount, and the falling DLL clock output unit 45 outputs clock signals (FCKDLL15, FCKDLL25) having a different delay amount.
The rising DLL clock output unit 44 includes an inverter IV1 which inverts an output signal of the NOR gate 42, and delay units D1 and D2 which both delay a signal of the inverter IVY for a predetermined period of time but which output the signal of the inverter Iv1 with a different delay amount.
The falling DLL clock output unit 45 includes an inverter IV2 which inverts and outputs an output signal of the NOR gate 43, and delay units D3 and D4 which both delay a signal of the inverter IV2 for a predetermined period of time but which output the signal of the inverter IV2 with a different delay amount.
The ODT control signal generation unit 50 receives an ODT signal ODT for controlling the ON or OFF status of an ODT resistor and generates and outputs an ODT control signal ODTLAT in synchronization with the internal clock signal iCLK and DLL clocks (RCKDLL10, RCKDLL20, FCKDLL15, FCKDLL25). The final outputted ODT control signal ODTLAT controls the ON or OFF status of an ODT resistor.
The ODT control signal generation unit 50 includes a plurality of latch circuits having an internal ODT signal iODT as an input, and a plurality of transmission gates being controlled by DLL clock signals (RCKDLL10, RCKDLL20, FCKDLL15, FCKDLL25). Any person skilled in the art can create the ODT control signal generation unit 50 in a variety of ways, and therefore a detailed explanation of the ODT control signal generation unit 50 is omitted.
According to such a prior art, during a power-down mode, it cannot output a normal clock since an ODT enable signal ODTEN is disabled and an inverted ODT enable signal ODTENB being inputted to NOR gates 42 and 43 of the DLL control unit 40 is fixed to a high level.
Accordingly, during a power-down mode, accurate control cannot be achieved as is possible in a normal mode, and the time for activating the ODT control signal ODTLAT cannot be controlled at the desired point of time.